AT86RF232
The leftmost bit (b 0 ) is transmitted first in time. The FCS is in this case
0010 0111 1001 1110.
The leftmost bit (r 0 ) is transmitted first in time.
8.2.3 Automatic FCS generation
The automatic FCS generation is activated with register bit TX_AUTO_CRC_ON = 1
(reset value). This allows the Atmel AT86RF232 to compute the FCS autonomously.
For a frame with a frame length specified as N (3 ≤ N ≤ 127), the FCS is calculated on
the first N -2 octets in the Frame Buffer, and the resulting FCS field is transmitted in
place of the last two octets from the Frame Buffer.
If the radio transceiver ’ s automatic FCS generation is enabled, the Frame Buffer write
access can be stopped right after MAC payload. There is no need to write FCS dummy
bytes.
In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the
ACK frame is always automatically generated by the AT86RF232, independent of the
TX_AUTO_CRC_ON setting.
Example:
A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a
Frame Buffer write access of five bytes (the last two bytes can be omitted). The first
three bytes are used for FCS generation; the last two bytes are replaced by the
internally calculated FCS.
8.2.4 Automatic FCS check
An automatic FCS check is applied on each received frame with a frame length N ≥ 2.
Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set if the FCS of a received
frame is valid. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and
remains valid until the next TRX_END interrupt caused by a new frame reception.
In RX_AACK mode, if FCS of the received frame is not valid, the radio transceiver
rejects the frame and the TRX_END interrupt is not issued.
In TX_ARET mode, the FCS and the sequence number of an ACK is automatically
checked. If one of these is not correct, the ACK is not accepted.
85
8321A – MCU Wireless – 10/11
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